Contents:
** Notes: * In timing diagrams, In/Out/InOut specifies port direction * SI/SO/SC/SD are the lines used by the gba com port - see section 4aSIO Normal 32bit mode (2 devices)
** Short description: This mode is generally used by devices attached directly to the gba, as it's capable of very high speeds (up to 2 mbit/sec). It could potentially be used for gba->gba comms, but it's not a good idea, in my opinion. ** Connection information: A proper connection is wired as follows: Master - Slave SC - SC SI - SO SO - SI it doesn't matter what SD is, it's never used in this mode. ** Timing Example: master is sending binary 10101010101010101010101010101110 slave is sending binary 11010101010101010101010101010110 Master: (bit #) 0 1 2 3 30 31 _________ __ __ __ __ __ __ ______ OUT SC |__| |__| |__| |__| ... |__| |__| _______________ _____ ________ ____ OUT SO 1 |__0__| 1 |_____... 1 |__0_| ____ ___________ ____ _________ ___ IN SI |_____| 1 1 |_0___| ... 1 |_0__| | | | | | A B C D E Slave: (bit #) 0 1 2 3 30 31 _________ __ __ __ __ __ __ ______ IN SC |__| |__| |__| |__| ... |__| |__| ____ ___________ ____ _________ ___ OUT SO |_____| 1 1 |_0___| ... 1 |_0__| _______________ _____ ________ ____ IN SI 1 |__0__| 1 |_____... 1 |__0_| | | | | | A B C D E ** Complete description: during IDLE (no transfer), the slave should set SO=HIGH, this signifies "not ready" when the slave is ready for transfer, the slave sets SO=LOW (A) when the master detects that SO is LOW, it pulls the clock low to signal the start of a transfer. (B) every time the clock makes a HIGH->LOW transition, both devices shift a bit out of the top of their shift register, onto their SO line (example: B) every time the clock makes a LOW->HIGH transition, both devices shift the bit they see on the SI line into the bottom of their shift register (example: C) after the 32nd bit, the master again forces SC to HIGH, both devices should return their SO lines to "high" asap. (E) there is probably a delay after the clock pulse takes place and the actual event occurs, however I can't test that at the moment, so such delays are shown just as a very likely possibility. (D, and slave's SO being offset) please note bits are transferred from MSB to LSB!
** Short Description:
The 16bit multiplay mode on Gameboy Advance allows a GBA to easily communicate
with up to 3 other gbas for the purpose of multiplayer gaming. It is a widely
used general purpose communication mode with a large number of uses.
** Connection Information
The gba multiplay link cables are wired as follows:
Master - Slave - Connector
SC - SC - SC
SD - SD - SD
SI (not connected)
SO - SI
SO - SO
SI (not connected)
When daisy chaining, the "master" of the second link cable is plugged into the
first link cable, which produces the following:
GBA0-GBA1-GBA2-GBA3
SC - SC - SC - SC
SD - SD - SD - SD
SI (Not connected)
SO - SI
SO - SI
S0 - SI
SO (Not connected)
Since the master's SI pin is unconnected, it reads as LOW, and since all GBAs in
this mode are outputting SO=HIGH, we can easily determine which gba is master.
This proves to be very useful, as the master is in control of the clock.
** Timing information:
Here's the general flow of things, a "zoomed out" view, as the document isn't
wide enough to properly show all of the timing waveform (nor do I want to
type that much)
Sample Timing: (SI_0 - SI_3 are the SI pins' state on each gba, if they exist)
_ _
SC |_____________________________________________________________________|
__ _ _ _ __
SD _AAAAAAAAAAAAAAA _BBBBBBBBBBBBBBBB _CCCCCCCCCCCCCCCC _DDDDDDDDDDDDDDD
__________________ _
SI_0 |____________________________________________________|
____________________________________ _
SI_1 |__________________________________|
______________________________________________________ _
SI_2 |________________|
_______________________________________________________________________ _
SI_3 _
Ok, that's a bit confusing. consider each character to be 1 bit, that's exactly
how the transfer works (minus timing accuracy, and all)
** Complete description:
SC gets set LOW by the master when the start bit is set in SIOCNT, the master
begins it's 16bit data transfer, then signals for the second gba, and so on.
when the 3rd transfer has completed (or the time allocated for it has elapsed)
the SC line is reset to high, and the transfer is completed. Interrupts are
generated on the gba at that point if they're requested.
In this diagram, the 16 A's is GBA0's 16bit data, B's are GBA1, C's are gba2,
and D's are GBA3. If any gba isn't present, SD stays high and their data is
0xffff
It's a basic set of 16bit UART transfers on SD, each gba transmits it's 18bit
message in turn (1 start + 16bit data, 1 stop) then sets it's SO bit to HIGH
signalling the next gba to begin it's transfer. the UART transfer speed is
determined by the actual gba hardware, and is set by the gba software.
(Looing at GBA)
__________________
/_______________/
| /_ _ _ _ _ /|
| /2_/_4_/_6_//|
| ===========/ |
\ -1- -3- -5- /
\___/ / /___/
|/__|
(Looking at cable)
_________________
/ __________ \
| / /\ |
| /__________/ \ |
|/___________\ /| |
/|_6_|_4_|_2_|\// |
||___/___/___||/ |
\|_5_|_3_|_1_|/___/
\____ ____/
---
Pin Numbers:
1: V+ (3.3v)
2: SO
3: SI
4: SD
5: SC
6: GND